1. Field of the Invention
The present invention relates to a signal processing circuit used in a digital serial interface.
2. Description of the Related Art
In recent years, as an interface for transfer of multimedia data, the IEEE (Institute of Electrical and Electronic Engineers) 1394, High Performance Serial Bus for realizing high speed data transfer and real time transfer has become the standard.
The types of data transfer of this IEEE 1394 serial interface include asynchronous transfer for requests, requests for acknowledgement, and confirmation of reception of the related art and isochronous transfer with which the data is sent at one time from a certain node at 125 xcexcs.
In this way, with an IEEE 1394 serial interface having such two transfer modes, data is transferred in units of packets.
FIGS. 11A and 11B are views of the byte size of a source packet in isochronous communication. FIG. 11A shows the size of a packet in the digital video broadcast (DVB) method; while FIG. 11B shows the size of a packet in the digital satellite system (DSS) method.
The source packet in the DVB method is comprised of 192 bytes, that is, 4 bytes of a source packet header (SPH) and 188 bytes of inherent transport stream data (TSD), as shown in FIG. 11A.
Contrary to this, the source packet in the DSS method is comprised of 144 bytes, that is, 4 bytes of a source packet header (SPH), 10 bytes of additional data (AD0 to AD9), and 130 bytes of inherent transport stream data (TSD) as shown in FIG. 11B.
The additional data is inserted between the source packet header and the transport stream data. Note that, in the EEE 1394 standard, the unit of minimum data able to be handled is one quadlet (=4 bytes=32 bits), therefore the transport stream data and the additional data must be set to be comprised in total of at least 32 bit units.
Note that at the default, no additional byte is set.
FIG. 12 is a view of an example of a correspondence between the original data when data is transmitted in the isochronous communication of the IEEE 1394 standard and the packets actually transmitted.
As shown in FIG. 12, each of the source packets of the original data is given a source packet header of 4 bytes and padding data for adjusting the data length and then is divided into a predetermined number of data blocks.
Note that since the unit of data when transferring a packet is one quadlet (4 bytes), the byte lengths of data blocks, various headers, etc. are all set to multiples of 4.
FIG. 13 is a view of the format of the source packet header.
As shown in FIG. 13, in 25 bits in the source packet header is written a time stamp utilized for suppressing jitter when for example MPEG (Moving Picture Experts Group)-TS (Transport Stream) data utilized in a digital satellite broadcast etc. of the above DVB method is transmitted by isochronous communication.
Such a packet header, a common isochronous packet (CIP) header, or other data is then added to a predetermined number of data blocks so as to produce the final packets.
FIG. 14 is a view of an example of the basic configuration of an isochronous communication use packet.
As shown in FIG. 14, in a packet for isochronous communication, the first quadlet is comprised of a 1394 header, the second quadlet a Header-CRC, the third quadlet a CIP-header 1, the fourth quadlet a CIP-header 2, the fifth quadlet a source packet header (SPH), and the sixth quadlet and subsequent quadlets the data regions. The final quadlet is a Data-CRC.
The 1394 header is comprised by a xe2x80x9cdata-lengthxe2x80x9d representing the data length, a xe2x80x9cchannelxe2x80x9d indicating number of the channel (one of 0 to 63) transferred through this packet, a xe2x80x9ctcodexe2x80x9d representing a code of processing, and a synchronous code xe2x80x9csyxe2x80x9d prescribed by each application.
The Header-CRC is an error detection code of the packet header.
The CIP-header 1 is comprised by a source node ID (SID) region for the transmission node number, a data block size (DBS) region for the length of the data block, a fraction number (FN) region for the number of divisions of the data in the formation of the packet, a quadlet padding count (QPC) region for the number of the quadlets of the padding data, a source packet header (SPH) region for the flag showing the existence of the source packet header, and a data block continuity counter (DBC) region for the counter for detecting the number of isochronous packets.
Note that the DBS region shows the number of the quadlets transferred through one isochronous packet.
The CIP-header 2 is comprised by an FMT region for the signal format showing the type of the data to be transferred and a format dependent field (FDF) region utilized corresponding to the signal format.
The SPH header has a time stamp region in which is set a value obtained by adding a fixed delay value when the transport stream packet.
Further, the data CRC is the error detection code of the data field.
The signal processing circuit of the IEEE 1394 serial interface for the transmission and reception of packets having the above structure is mainly constituted by a physical layer circuit for directly driving the IEEE 1394 serial bus and a link layer circuit for controlling the data transfer of the physical layer circuit.
In the isochronous communication system in the IEEE 1394 serial interface, as shown In for example FIG. 15, the link layer circuit 2 is connected to an application, that is, MPEG transporter 1, while the link layer circuit 2 is connected to a serial interface bus BS via a physical layer circuit 3.
In the transfer of data of the IEEE 1394 serial interface, the transmission data and reception data are stored once in a storage device such as a first-in first-out (FIFO) memory (hereinafter simply referred to as an FIFO) provided in the link layer circuit 2. In actuality, an asynchronous packet use FIFO and an isochronous packet use FIFO are separately provided.
As shown in FIG. 11, however, the size of a source packet of a normal MPEG transport stream is changeable, for example, 192 bytes in the DVB and 144 bytes in the DSS.
On the other hand, the size of the FIFO provided in the link layer circuit is set. Therefore, when there is an error in the source packet which is received, it may be considered to propagate the error around the FIFO by providing a register with several consecutive error bits separate from the FIFO.
In this case, however, a separate circuit has to be provided to make it known which source packet stored in the FIFO the error bit is for. This has the disadvantage that the size of the circuit becomes larger.
Further, when using isochronous communication to transmit MPEG-TS data used in the above-mentioned DVB system or other digital satellite broadcasting, the signal processing circuit on the reception side must output transport stream data to the so-called application side that is, the MPEG transporter, based on the time side by the time stamp added to the packet.
In current IEEE 1394 serial interface signal processing circuits, however, no processing system has yet been established for the time stamp added to the received packet.
For example, the case may be considered where an unpredictable value of the time stamp not possible is set and transmitted due to blurring of data or the connection of different systems. It is consequently necessary to establish a system which can operate stably without stopping even in this case.
Further, it is necessary to realize a circuit which can output a packet immediately after a time set for the application side or reception.
Further, when using isochronous communication to transmit MPEG-TS data used in the above-mentioned DVB system or other digital satellite broadcasting, the transmission side signal processing circuit adds a delay in accordance with the amount of data to the time stamp to be added to the packet.
This delay is set to a small value when the amount of the image or other data increases. The reception side outputs transport stream data to the so-called application side that is, the MPEG transporter.
The reception side stores the received data once in an FIFO or other storage device. The smaller the delay set in accordance with the amount of data at the transmission side, the shorter the time from reception to when the transport stream data to the MPEG transporter is output.
As explained above, however, since there is no system for processing the time stamp added to the packet in current IEEE 1394 serial interface signal processing circuits, when for example the channel is changed and the amount of data increases unnecessary data ends up being output to the application side regardless of the change of the channel. Alternatively, while the data with a large delay of a time stamp before the change of channel is being stored in the FIFO without being output yet from the reception side, there is the danger that the next data with a small delay will be stored in the FIFO, the positional relationship of the data will be ruined, and overflow or other problems will occur.
A first object of the present invention is to provide a signal processing circuit which can simply set an error bit without increasing the size of the circuit even with different sizes of source packets and which can realize stable operation without the system stopping even if the time stamp is of a nonexistence value.
A second object of the present invention is to provide a signal processing circuit which can accurately add time information.
A third object of the present invention is to provide a signal processing circuit which can output a packet in a time set for the application side.
A fourth object of the present invention is to provide a signal processing circuit which can prevent damaged data or unnecessary data from being output to the application side even when the time information set in accordance with the amount of data is changed.
To achieve the above object, according to a first aspect of the present invention, there is provided a signal processing circuit for receiving packet data transmitted through a serial interface bus in a predetermined time cycle and outputting the packet data to an application side, comprising a memory means; a first reception circuit for receiving transmitted packets, deciding whether every received packet is transmitted according to the standard, adding an error mark when it is not according to the standard, and storing the result in the memory means; and a second reception circuit for performing process according to the error and outputting the result to the application side when an error mark is added to packet data stored in the memory means.
Preferably, the packets transmitted over the serial bus are given control information indicating whether the transmitted packets are continuous or not; the first reception circuit adds the error mark when deciding from the control information that the received packets are not continuous; and the second reception circuit outputs an error packet to the application side in place of the packet data stored in the memory means when an error mark is added.
Preferably, each of the source packets transmitted over the serial bus is given a source packet header containing time information set with a time for the reception side to output the received data to the application side; the first reception circuit adds the error mark when the time information indicates a time exceeding a predetermined time; and the second reception circuit outputs the packet data stored in the memory means regardless of the time information where an error mark is added.
According to the signal processing circuit of the present invention, the first reception circuit decides if each received packet has been transmitted according to the standard, adds an error mark to a received packet when not according to the standard, and stores the result in the memory means.
Further, the second reception circuit performs processing for the error and outputs the result to the application side when an error mark is added to packet data stored in the memory means.
Alternatively, according to the present invention, the packets transmitted over the serial bus are given control information indicating whether the transmitted packets are continuous or not. The reception circuit adds the error mark when deciding from the control information that the received packet are not continuous.
Further, the second reception circuit outputs an error packet to the application side in place of the packet data stored in the memory means when error mark is added.
Alternatively, according to the present invention, each of the source packets transmitted over a serial interface bus is given a source packet header containing time information set with a time for a reception side to output received data to an application side. The first reception circuit adds an error mark when the time information indicates a time exceeding a predetermined time.
Further, the second reception circuit outputs the data stored in the memory means regardless of the time information when the error mark is added.
According to a second aspect of the invention, there is provided a signal processing circuit for adding to the packet data information pertaining to the time during which a reception side outputs received data to the application side and transmitting the result over a serial interface bus in a predetermined time cycle, comprising a counting means for counting the time; a control means able to set a delay time to be added according to the amount of transmission data; a memory means; a first transmission circuit for adding the time information to transmission data based on the delay time set by the control means and storing the result in the memory means; and a second transmission circuit for setting a threshold for deciding whether transmission of a packet is valid or not according to the amount of transmission data, deciding whether the set time information is valid or not from the set threshold, the time information stored in the memory means, and the time counted by the counting means, reading the packet data given the time information and transmitting it as the transmission data when valid, and not reading the packet but processing the next packet when it is invalid.
According to the signal processing circuit of the invention, the first transmission circuit adds the time information to the transmission data based on the delay time set by the control means and stores the result in the memory means.
Further, the second transmission circuit sets a threshold in accordance with the amount of transmission data for deciding if the transmission of the packet is valid and deciding if the set time information is valid or not by the set threshold, the time information stored in the memory means, and the time counted by the counting means.
When the result of the decision is that the transmission is valid, the packet data given the time information is read and transmitted as the transmission data.
When the transmission is invalid, the packet is not read and the next packet is processed.
According to third aspect of the present invention, there is provided a signal processing circuit for receiving packet data given time information set with a time for the reception side to output the received data to the application side and for receiving packet data transmitted over a serial interface bus and outputting the result to the application side in a predetermined time cycle, comprising a counting means for counting time and a reception circuit for reading the time information from the received packet data and outputting the received data to the application side when the time counted by the counting means is larger than the value of the time information.
Preferably, the reception circuit comprises a memory means; a pre-processing circuit for restoring data from the received packet data, storing this in the memory means with the time information, and outputting a stored information signal; a comparison circuit for receiving the stored information signal of the pre-processing circuit, reading the time information stored in the memory means, comparing the time information and the time counted by the counting means, and outputting a data read instruction signal when the count is larger; and a data read control means for reading data stored in the memory means and outputting the same to the application side if receiving the data read instruction signal.
According to a fourth aspect of the present invention, there is provided a signal processing circuit for receiving packet data given time information set with a time for a reception side to output received data to an application side and transmitted over a serial interface bus in a predetermined time cycle and outputting the result to the application side, comprising a reception circuit for outputting the received data to the application side when the time information of the received packet data indicates a time exceeding a predetermined time.
According to a fifth aspect of the present invention, there is provided a signal processing circuit for receiving packet data given time information set with a time for a reception side to output received data to an application side and transmitted over a serial interface bus in a predetermined time cycle and outputting the same to the application side, comprising a counting means for counting time and a reception circuit for reading the time information from the received packet data and outputting the received data to the application side when the time counted by the counting means is larger than the value of the time information or the time information indicates a time exceeding a predetermined time.
Preferably, the reception circuit comprises a memory means; a pre-processing circuit for restoring data from the received packet data, storing the result in the memory means with the time information, and outputting a stored information signal; a comparison circuit for receiving the stored information signal of the pre-processing circuit, reading the time information stored in the memory means, comparing the time information and the time counting by the counting means, and outputting a data read instruction signal when the count is larger; a decision circuit for deciding whether the time information indicates a time exceeding a predetermined time or not and outputting a data read instruction signal when exceeding it; and a data read control means for reading the data stored in the memory means and outputting the result to the application side if receiving the data read instruction signal of the comparison circuit or the decision circuit.
According to the signal processing circuit of the present invention, time information is fetched from the packet data received by the reception circuit and the received data is output to the application side when the value of the time counted by the counting means is larger than the value of the time information.
Further, the received data is output to the application side when the time information of the received packet data indicates a time exceeding a predetermined time.
According to a sixth aspect of the present invention, there is provided a signal processing circuit for receiving packet data given time information set with a time for a reception side to output received data to an application side and transmitted over a serial interface bus in a predetermined time cycle and outputting the result to the application side, comprising a control means for outputting the received data to the application side regardless of the time information of the received packet data.
According to a seventh aspect of the present invention, there is provided a signal processing circuit for receiving packet data given time information set with a time for a reception side output received data to an application side and transmitted over a serial interface bus in a predetermined time cycle and outputting the result to the application side, comprising a counting means for counting time; a reception circuit for reading the time information from the received packet data and outputting the received data to the application side when the value counted by the counting means is larger than the value of the time information: and a control means for causing the reception circuit to output the received data to the application side regardless of the time information by a control signal.
Preferably, the reception circuit comprises a memory means; a pre-processing circuit for restoring data from the received packet data, storing the result in the memory means with the time information, and outputting a stored information signal; a comparison circuit for receiving the stored information signal of the pre-processing circuit, reading the time information stored in the memory means, comparing the time information and the value of the time counted by the counting means, and outputting a data read instruction signal when the count is larger; and a data read control means for reading the data stored in the memory means and outputting it to the application side when receiving the data read instruction signal and receiving the received data stored in the memory means and outputting it to the application side regardless of the time information based on the stored information signal when receiving a control signal from the control means.
According to the signal processing circuit of the present invention, the control means outputs the received data to the application side regardless of the time information of the received packet data.
Further, according to the present invention, the time information is fetched from the received packet data and the received data is output to the application side when the value of the time counted by the counting means is larger than the value of the time information. Further, the control means causes the reception circuit to output the received data to the application side regardless of the time information.
According to an eighth aspect of the present invention, there is provided a signal processing circuit for adding information pertaining to a time for a reception side to output received data to an application side to packet data and transmitting the result over a serial interface bus in a predetermined time cycle, comprising a control means able to set a delay time to be added according to an amount of transmission data; a memory means; a first transmission circuit for adding the time information to the transmission data based on the delay time set by the control means, storing the result in the memory means, and outputting a stored information signal; a comparison circuit for comparing a previously set delay time from the control means and a newly set delay time and outputting a data read control signal when the newly set delay time is shorter; and a second transmission circuit for receiving the stored information signal of the first transmission circuit, reading packet data containing time information stored in the memory means, outputting this as transmission data, and, when receiving the data read control signal, reading packet data given time information based on the newly set delay time and outputting it as transmission data.
Preferably, further it comprises a latch circuit for latching the delay time set by the control means; the first transmission circuit adds the time information based on the delay time latched by the latch circuit; and the comparison circuit compares the delay time set by the control means and the delay time latched by the latch circuit.
According to the signal processing circuit of the present invention, the first transmission circuit adds time information to the transmission data based on a delay time set by the control means, stores the result in the memory means, and outputs a stored information signal to the second transmission circuit.
The comparison means compares the delay time previously set by the control means and a newly set delay time and outputs a data read control signal to the second transmission circuit when the newly set delay time is shorter.
The second transmission circuit receives the stored information signal of the first transmission circuit, reads the packet data containing the time information stored in the memory means, and transmits the result as the transmission data.
When receiving a data read control signal from the comparison circuit, the packet data given the time information based on the newly set delay time is read and transmitted as the transmission data.